1. Technical Field of the Invention
The invention relates generally to communication systems; and, more particularly, it relates to decoding of encoded signals within such communication systems.
2. Description of Related Art
Data communication systems have been under continual development for many years. One such type of communication system that has been of significant interest lately is a communication system that employs turbo codes. Another type of communication system that has also received interest is a communication system that employs Low Density Parity Check (LDPC) code. A primary directive in these areas of development has been to try continually to lower the error floor within a communication system. The ideal goal has been to try to reach Shannon's limit in a communication channel. Shannon's limit may be viewed as being the data rate to be used in a communication channel, having a particular Signal to Noise Ratio (SNR), that achieves error free transmission through the communication channel. In other words, the Shannon limit is the theoretical bound for channel capacity for a given modulation and code rate.
LDPC code has been shown to provide for excellent decoding performance that can approach the Shannon limit in some cases. For example, some LDPC decoders have been shown to come within 0.3 dB from the theoretical Shannon limit. While this example was achieved using an irregular LDPC code of a length of one million, it nevertheless demonstrates the very promising application of LDPC codes within communication systems.
In performing calculations when decoding a received signal within such communication systems, it is common for these decoders to perform interleaving and/or de-interleaving of the received data to some degree. The memory required and the memory management required to do this interleaving is oftentimes quite difficult. For example, the amount of memory required to store the interleaver pattern (the interleaver pattern memory) is typically very large. In addition, the actual interleaver memory that is employed to perform the writing and reading of the received symbols according to the interleaver pattern is also typically quite large. The prior art approach to support such interleaving is to employ dual port memory devices.
FIG. 1A is a diagram illustrating a prior art dual port memory structure. A dual port memory device allows for two simultaneous read and write operations to be performed to the memory. For example, a write access may be performed to the memory at one location at the same time that a read access may be performed to the memory at another location. These dual port memory structures are oftentimes typically quite large in area (real estate) and oftentimes quite expensive. For communication systems where area and/or cost are important design directives, the use of dual port memory structures may be inherently prohibited. However, as is discussed below, the use of single port memory structures is insufficient to meet the needs within communication systems.
FIG. 1B is a diagram illustrating a prior art single port memory structure. In contradistinction to the dual port memory structure described above, a single port memory structure will allow only one memory access operation at a time (be it read or write). These single port memory structures are typically much cheaper in cost than the dual port memory structures described above. However, prior art decoding techniques that employ interleaving oftentimes need to operate at such high speeds that single port memory devices cannot be used. As data rates continue to increase within such communication systems, there appears in the prior art no place for single port memory devices to be used within the interleaving processing given that the current direction of development within communication systems is towards higher operational speeds and higher amounts of throughput.